This invention relates to a semiconductor read-only memory (hereinbelow, termed "ROM"), and more particularly to a longitudinal type ROM.
As disclosed in, for example, the specification of U.S. Pat. No. 4,240,151, a longitudinal type ROM constituting a logic block (memory array) is constructed of a plurality of insulated-gate field effect transistors (hereinbelow, termed "MISFETs") which are connected in series. Each of the plurality of series MISFETs is made the depletion mode or the enhancement mode, depending upon the information to be written into the memory.
More specifically, among the MISFETs connected in series, one to be switched and controlled by an input signal is made the enhancement mode, and one not to be switched and controlled by an input signal is made the depletion mode.
The longitudinal type ROM has features as stated below. The source of one of the MISFETs adjacent to each other and the drain of the other MISFET are electrically connected in common. Accordingly, the source semiconductor region of one MISFET and the drain semiconductor region of the other MISFET which are formed in a single semiconductor substrate by the semiconductor integrated circuit technology can be constructed of a common semiconductor region. Since the source region and drain region of the adjacent MISFETs can be connected without using an evaporated aluminum interconnection layer or the like, a contact area on the semiconductor substrate can be reduced. In a semiconductor integrated circuit (IC), accordingly, the ROM can be formed to occupy a comparatively small area. The longitudinal type ROM is suitable especially in a case where the IC is constructed of MISFETs, such as silicon gate MISFETs, in which the source region and the drain region are formed in self-alignment with the gate electrode.
In the longitudinal type ROM, however, it must be attended to that the MISFETs in a number corresponding to the number of input terminals of the ROM are connected in series, that the "on" resistance value of the entire series connection of the MISFETs becomes a comparatively great value, and that parasitic capacitances which limit the operating speed of the circuit increase due to an increase in the number of the MISFETs.
In, for example, a longitudinal type ROM which is employed as an OR array in a PLA (programmable logic array), a comparatively large number of MISFETs are connected in series in correspondence with the number of input terminals of the ROM. As a result, the "on" resistance value of the whole series connection of the MISFETs becomes conspicuously great, and the parasitic capacitances increase. When the number of the input terminals to be supplied with address signals has increased in this manner, the read speed of data lowers.
By way of example, in order to fabricate a ROM having program addresses of 256 steps, 256 series MISFETs are required.
The problem concerning the speed can be solved by the use of a divided type longitudinal ROM which is disclosed in, for example, the official gazette of Japanese Laid-open Patent Application No. 53-80931. In this ROM, MISFETs to be supplied with input signals are divided into a plurality of groups, and output signals from the serially-connected MISFETs in the respective groups are logically combined by logic circuits. The divided type longitudinal ROM exhibits comparatively-high operating speed characteristics because the number of the MISFETs to be connected in series is reduced.
It has been revealed, however, that when the divided type longitudinal ROM is put into the form of an IC, circuit is liable to malfunctions on account of the undesirable capacitance coupling between one circuit node and another circuit node.